Subject: RE: [sv-bc] proposal for nested modules and interfaces
From: Stuart Sutherland (stuart@sutherland-hdl.com)
Date: Mon Jan 05 2004 - 10:20:12 PST
I did some testing on this for book on SV I wrote. Currently, it appeared
to me that software tools that have implemented nested modules ignore them
if they are not instantiated. Personally, I think that is both an intuitive
and a useful behavior. If a nested module has no ports, and it is
implicitly instantiated, then it must be hardcoded to use the signal names
in its parent module. Hardcoded names is not a good style for design
re-use, and not one that the standard encourage through implicit
instantiation. If a nested module does have ports, and it is implicitly
instantiated, then what gets hooked to the ports? At best, it would have to
infer an implicit instance with a .* port list, which is currently not
synthesizable.
I think uninstantiated nested modules should be ignored, the way they are
now.
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
503-692-0898
> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Dave Rich
> Sent: Monday, January 05, 2004 8:37 AM
> To: sv-bc@eda.org
> Subject: [sv-bc] proposal for nested modules and interfaces
>
> In section 18.6 nested modules, add the following paragraph after
>
> This allows the same module name, e.g. and2, to occur in
> different parts of the design and represent different
> modules. Note that an alternative way of handling this
> problem is to use configurations.
>
> _Nested modules with no ports that are not explicitly
> instantiated shall be implicitly instantiated once.
> Otherwise, if not explicitly instantiated, they are ignored._
>
>
>
> --
> --
> David.Rich@Synopsys.com
> Technical Marketing Consultant
> http://www.SystemVerilog.org
> tele: 650-584-4026
> cell: 510-589-2625
>
>
>
>
>
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