Subject: Re: [sv-bc] proposal for nested modules and interfaces
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Jan 05 2004 - 10:23:09 PST
Yes, I agree that it should be noted.
Nested modules with no ports that are not explicitly instantiated shall
be implicitly instantiated once with an instance name identical to the
module name. Otherwise, if not explicitly instantiated, they are ignored.
Shalom Bresticker wrote:
>Dave,
>
>Do you want to say something like,
>"implicitly instantiated with an instance name identical to the module name"?
>
>Shalom
>
>
>Dave Rich wrote:
>
>
>
>>In section 18.6 nested modules, add the following paragraph after
>>
>>This allows the same module name, e.g. and2, to occur in different parts
>>of the design and represent different modules. Note that an alternative
>>way of handling this problem is to use configurations.
>>
>>_Nested modules with no ports that are not explicitly instantiated shall
>>be implicitly instantiated once. Otherwise, if not explicitly
>>instantiated, they are ignored._
>>
>>--
>>--
>>David.Rich@Synopsys.com
>>Technical Marketing Consultant
>>http://www.SystemVerilog.org
>>tele: 650-584-4026
>>cell: 510-589-2625
>>
>>
>
>--
>Shalom Bresticker Shalom.Bresticker@motorola.com
>Design & Reuse Methodology Tel: +972 9 9522268
>Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
>POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
>
>
>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625
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