Subject: [sv-bc] requirement for "exact match" of types
From: Paul Graham (pgraham@cadence.com)
Date: Mon Jan 05 2004 - 11:07:35 PST
The LRM does not define exact matching of types. Furthermore, section 5.8
says:
Note that there is no category for identical types defined here because
there is no construct in the SystemVerilog language that requires
it. For example, as defined below, int may can be interchanged with bit
signed [0:31] wherever it is syntactically legal to do so. Users may can
define their own level of type identity by using the $typename system
function (see Section 22.2, Typename function), or through use of the
PLI.
However, sections 7.13 and 7.14 refer to "exact" type matches:
7.13:
For type:value, if the element or sub array type of the unpacked array
exactly matches this type, then each element or sub array shall be set
to the value.
7.14:
The type:value specifies an explicit value for a field in the structure
which exactly matches the type and has not been set by a field name
specifier above.
Can I assume that an exact type match means a match of type identifiers? By
this rule, "int" exactly matches "int" and nothing else. In particular,
"int" does not exactly match "bit signed [31:0]", despite the language of
section 5.8.
Or does "exact match" refer to one of the other forms of type compatibility
listed in section 5.8?
Paul
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