Subject: RE: [sv-bc] proposal for nested modules and interfaces
From: Steven Sharp (sharp@cadence.com)
Date: Mon Jan 05 2004 - 11:18:42 PST
>If you are writing the nested module to encapsulate some
>piece of local functionality, and you need that functionality
>only once, it seems pretty silly to have to instantiate it
>immediately after defining it.
And having a module instance appear when you didn't intentionally
instantiate one is pretty surprising. Surprising is much worse
than silly.
The most likely reason to create a nested module is to re-use it
in multiple instantiations, not to encapsulate a single instance.
If somebody wants to encapsulate one instance of some local
functionality, they can already encapsulate the code inside a
named generate block, with no need for a nested module.
And speaking of generates, your idea of when these implicit
instantiations occurs needs some work. Consider a nested
module that gets instantiated inside a generate-loop. For
some parameter values it might get instantiated multiple times,
for others just once. And in some end cases for some parameter
values, it might get instantiated zero times because none are
needed. Are you suggesting that it should then get implicitly
instantiated once? And that there is no way to make it get
instantiated zero times, even though that is what you really want
in that case?
>It also matches with the way modules get instantiated
>into $root (or whatever $root is called these days!); any
>uninstantiated portless module is a top-level and is
>therefore implicitly instantiated in the elaborated
>simulation. So, all your regular modules are in fact
>merely nested modules in $root...
Uninstantiated modules WITH ports are also top-level, so what
you are proposing does NOT match existing behavior. And with
Verilog-2001 configs, there is now a way to explicitly specify
what modules get instantiated as top-level modules, instead of
relying on this older implicit mechanism.
Steven Sharp
sharp@cadence.com
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