Subject: Re: [sv-bc] proposal for nested modules and interfaces
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Jan 05 2004 - 13:14:25 PST
Hi Dave;
I'll ask the obvious question...
Why not exclude nested modules not instantiated? Why base its inclusion on the
absence of ports?
I can only see this as a verification thing - referencing signals in the outer
module through module name hierarchical references. Don't know what synthesis
tools should/would do with such a module.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-author "Assertion Based Design"
This archive was generated by hypermail 2b28 : Tue Jan 06 2004 - 03:29:16 PST