Subject: Re: [sv-bc] Is TIME integer or non_integer type?
From: Steven Sharp (sharp@cadence.com)
Date: Wed Feb 11 2004 - 16:19:32 PST
I just wanted to point out that in the Verilog language at least, the "time"
type has no actual connection to times. It is just another integral/vector
type that happens to be large enough to hold a simulation time. It has no
time-related semantics built in to it, unlike SystemVerilog time literals.
If "time" has some specific time-related semantics in SystemVerilog (such
as a special relationship to time literals), then this is a significant
departure from Verilog.
I am mentioning this because Nikhil mentioned time literals in a discussion
of the time type. As far as I can see, there is very little relationship
between them.
In the same way, in the Verilog language, there is no meaningful difference
between a real and a realtime.
Steven Sharp
sharp@cadence.com
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