Subject: [sv-bc] Review Items for Chapter 7
From: Maidment, Matthew R (matthew.r.maidment@intel.com)
Date: Thu Feb 12 2004 - 02:06:16 PST
7.11:
Change:
A field select is defined as a hierarchical name where the RHS of the
last "." hierarchy ...
To:
A field select is defined as a hierarchical name where the *right hand
side* of the last "." hierarchy
7.13:
Following this paragraph:
SystemVerilog determines the context of the braces by looking at the
left hand side
when used in the context of an assignment. If the left hand side is an
used in the
context of an assignment to an unpacked array, the braces represent an
unpacked array
literal or expression. Outside the context of an assignment on the
right hand side,
an explicit cast must be used with the braces to distinguish it from a
concatenation.
Please consider adding the following:
The following is considered illegal:
logic [2:0] a [1:0];
logic [2:0] b ,c;
always {b,c} = a; // illegal assignment the braces are not determined
to be an unpacked array expression.
7.14 - The replication operator is omitted from this section but
included in
section 2.8. The last sentence of the section implies it is allowed for
structure expressions:
"Of the type key, default key, or replication operator is used on an
expression
with side effects, the number of times that expression evaluates is
undefined."
Perhaps it should read:
"*I*f the type key, default key, or replication operator is used on an
expression
with side effects, the number of times that expression evaluates is
undefined."
Why not at least mention that replication is also a possibility?
What about changing the opening sentences:
"A structure expression (packed or unpacked) can be built from member
expressions using
braces and commas, with the members in declaration order. Each member
expression shall
be evaluated in the context of an assignment to the type of the
corresponding member
in the structure. It can also be built with the names of the members"
To:
"A structure expression (packed or unpacked) can be built from member
expressions using
braces and commas, with the members in declaration order. Replicate
operators can be used
to set the values for the exact number of members. Each member
expression shall
be evaluated in the context of an assignment to the type of the
corresponding member
in the structure. It can also be built with the names of the members"
7.15
Change:
(e.g., it is used in the RHS of an assignment
To:
(e.g., it is used in the right hand side of an assignment
7.18
To better demonstrate the compatibility of bit-stream operators
and bit-stream types:
Change:
int a, b, c;
bit [96:1] y = {>>{ a, b, c }}; // OK: pack a, b, c
int j = {>>{ a, b, c }}; // error: j is 32 bits < 96 bits
bit [99:0] b = {>>{ a, b, c }}; // OK: b is padded with 4 bits
{>>{ a, b, c }} = 23'b1; // error: too few bits in stream
{>>{ a, b, c }} = 96'b1; // OK: unpack a = 0, b = 0, c = 1
{>>{ a, b, c }} = 100'b1; // OK: unpack as above (4 bits unread)
To:
int a, b, c;
logic [10:0] up [3:0];
logic [11:1] p1, p2, p3, p4;
bit [96:1] y = {>>{ a, b, c }}; // OK: pack a, b, c
int j = {>>{ a, b, c }}; // error: j is 32 bits < 96 bits
bit [99:0] b = {>>{ a, b, c }}; // OK: b is padded with 4 bits
{>>{ a, b, c }} = 23'b1; // error: too few bits in stream
{>>{ a, b, c }} = 96'b1; // OK: unpack a = 0, b = 0, c = 1
{>>{ a, b, c }} = 100'b1; // OK: unpack as above (4 bits unread)
{>>{p1, p2, p3, p4}} = up //OK: unpack p1 = up[3], p2 = up[2], p3 =
up[1], p4 = up[0]
-- Matt Maidment mmaidmen@ichips.intel.com
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