[sv-bc] A possible problem in the BNF

Hello All,

Looking at the module declaration BNF (after implying the changes in LRM
243)

It looks like we disabled the use of nested ANSI-style port lists (that
are OK in V2K) such as

module m(input a,b , output reg c,d, input wire e,f )...// note that
'a' and 'b' share the same input direction

Also this implies such nested lists are not allowed in interface and
program ANSI-style declarations

The relevant BNF reads

module_nonansi_header ::=

{ attribute_instance } module_keyword [ lifetime ] module_identifier [
parameter_port_list ]

list_of_ports ;

list_of_port_declarations26 ::=

( [ { attribute_instance} ansi_port_declaration { , {
attribute_instance} ansi_port_declaration } ] )

ansi_port_declaration ::=

[ net_port_header | interface_port_header ] port_identifier {
unpacked_dimension }

| [ variable_port_header ] port_identifier variable_dimension [ =
constant_expression ]

| [ net_port_header | variable_port_header ] . port_identifier ( [
expression ] )

port_identifier ::= identifier

We might want to change the rule for the ansi_port_declaration in
section A.1.4 TO:

ansi_port_declaration ::=

[ net_port_header | interface_port_header ] list_of_port_identifiers

| [ variable_port_header ] list_of_variable_port_identifiers

| [ net_port_header | variable_port_header ] . port_identifier ( [
expression ] )

Note the following rules will not be changed

list_of_port_identifiers ::= port_identifier { unpacked_dimension }

{ , port_identifier { unpacked_dimension } }

list_of_variable_port_identifiers ::= port_identifier variable_dimension
[ = constant_expression ]

{ , port_identifier variable_dimension [ = constant_expression ] }

Does this look reasonable?

Dan Jacobi, Intel Corporation

Tel : +(972)-4-8655855

 
Received on Wed Mar 31 02:47:39 2004