Re: [sv-bc] FW: Clarification on unions (from Stu Sutherland)

From: Peter Flake <Peter.Flake@synopsys.com>
Date: Tue Apr 06 2004 - 09:47:21 PDT

Dave,

It is probably worthwhile adding that a packed union can be used like any
other packed object, since it is a like a vector.

So Stu's $display would be legal for a packed union but not for an unpacked
one.

Peter.

At 10:39 01/04/2004 -0800, you wrote:
>A regular (unpacked) union is an aggregate by the definition in section 3.13.
>
>That means as a whole, it can only be copied or compared to equivalent
>types. (and before anybody asks, the result of a comparison of two unions
>can not be defined because the alignment of members in the union is not
>defined)
>
>Whether or not it can be used in $display is a different story. At the
>last SV-BC meeting we discussed proposing an errata to bring all the file
>I/O routines up to spec with the rest of SV.
>
>Dave
>
>
>David W. Smith wrote:
>
>>-----Original Message-----
>>From: Stuart Sutherland [mailto:stuart@sutherland-hdl.com] Sent:
>>Thursday, April 01, 2004 7:58 AM
>>To: David.Smith@Synopsys.COM
>>Subject: Clarification on unions
>>
>>David,
>>
>>I'm not sure which subcommittee this question should go to. Could you
>>please forward this question to the right group?
>>
>>Is it legal to access a union using just the union name without a member
>>name? If so, what are the rules for what type is read from the union? For
>>example, is the following legal?
>>
>> union {
>> int unsigned u;
>> int s;
>> } foo;
>>
>> initial begin
>> foo.i = -5;
>> $display("foo = %d", foo); //is this reference to foo legal?
>> end
>>
>>I could not find anything in the LRM on this, for unpacked, packed or tagged
>>unions, although the following sentence might be on this topic (it is not
>>clear to me). It seems to me that this should be covered in section 3.11.
>>
>>Stu
>>~~~~~~~~~~~~~~~~~~~~~~~~~
>>Stuart Sutherland
>>stuart@sutherland-hdl.com
>>503-692-0898
>>
>>
>>
>
>--
>--
>David.Rich@Synopsys.com
>Technical Marketing Consultant and/or
>Principal Product Engineer
>http://www.SystemVerilog.org
>tele: 650-584-4026
>cell: 510-589-2625
>
>
Received on Tue Apr 6 09:49:17 2004

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