[sv-bc] name resolution of struct members

I could not find in the systemVerilog draft 6 anything that describes
enhanced name resolution rules.
A struct member name uses the . separator that is also used for
hierarchical names.
So it appears that we need to take this into account when doing name
resolution.
Currently in Verilog, if a . name is found we do downward and upward name
lookup trying to resolve the XMR.

So if I have a name "a.b.c" in a given scope and I have a struct variable
named "a" in that scope which has a "b" member which does not contain a "c"
member, is this a parser error because the trial failed or do we assume
that this is an XMR which will be resolved when the whole design is elaborated?

Francoise
        '
Received on Wed Apr 7 12:21:07 2004