> However, that is not how hierarchical name resolution works in Verilog-XL,
> or any implementation that matches it. If there is a match for the
> start of the name, but the entire name is not matched, the upward search
> continues. If there is a valid resolution anywhere, it will be found.
The section of 1364-2201 I quoted says:
"a) Look in the current module for a module instance named
module_instance_name. If found, this name reference shall be
treated as a downward reference, and the item name shall be
resolved in the corresponding module."
To me the "shall be treated as a downward reference" means that
this should be an error. If this is not what Verilog-XL does, is
this an error in the 1364 LRM or was this a deliberate change from the
Verilog-XL behavior?
Received on Wed Apr 7 16:53:50 2004
This archive was generated by hypermail 2.1.8 : Wed Apr 07 2004 - 16:53:52 PDT