RE: [sv-bc] name resolution of struct members

Mark,

this is exactly the case I was referring to.
I believe that first we should file an errata for fixing the text in
Verilog 2001
as to clarify the intent of name search rules in Verilog.
Then we can determine what would my case would do.

Steve,

did you file a 1364 errata?
Francoise
        '
At 05:59 PM 4/8/2004 -0400, Steven Sharp wrote:

> >To me the "shall be treated as a downward reference" means that
> >this should be an error. If this is not what Verilog-XL does, is
> >this an error in the 1364 LRM or was this a deliberate change from the
> >Verilog-XL behavior?
>
>This text did not appear in the Verilog-XL manual or the OVI standard,
>but was added in the IEEE standard. However, I find it extremely
>doubtful that this was a deliberate change. It is more likely that it
>was an attempt to describe the situation in more detail, which failed
>because English is a poor language for describing a complex algorithm.
>
>Note that the text has other problems as well. It only allows upwards
>name references for two-part names like a.b, not longer names like a.b.c.
>It refers to module_instance.item_name, where item_name is a grammar
>nonterminal that is defined in Syntax 12-8 and apparently allows only
>simple identifiers. So I wouldn't take a literal reading of the text
>too seriously.
>
>Steven Sharp
>sharp@cadence.com
Received on Fri Apr 9 07:12:27 2004