Re: [sv-bc] array of interfaces

Hi Paul,

The behavior of the connections to the of ports of an interface (and
program) are identical to that of a module. The answer is: it depends on
the definition of the port of my_intf. Existing Verilog rules apply.

Dave

Paul Graham wrote:

>For an array of interfaces instantiated with an interface port:
>
> wire [3:0] x;
> my_intf mi[3:0] (x);
>
>Does the port get sliced up among the different instances the way that
>it would with an array of instances? Or is the whole port connected
>to each instance? In other words, is the above equivalent to this:
>
> wire [3:0] x;
> my_intf mi[3](x[3]), mi[2](x[2]), mi[1](x[1]), mi[0](x[0]);
>
>or to this:
>
> wire [3:0] x;
> my_intf mi[3](x), mi[2](x), mi[1](x), mi[0](x);
>
>Paul
>
>
>
>

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