[sv-bc] RE: [sv-ec] Congratulation TEAM - SystemVerilog 3.1A Approved By Accellera Board

Greetings,
I would like to add both my thanks for the support and effort all of you have put into making SystemVerilog successful and
congratulations on bringing the development 3.1a to approval.

Regards
David

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of Vassilios.Gerousis@infineon.com
Sent: Thursday, April 29, 2004 9:22 AM
To: sv-ac@eda.org; sv-bc@eda.org; sv-cc@eda.org; sv-ec@eda.org
Subject: [sv-ec] Congratulation TEAM - SystemVerilog 3.1A Approved By Accellera Board

Dear SystemVerilog Members,
        SystemVerilog 3.1A has been approved by 11 yes and three
abstentions (Cadence, Verisity, and IBM). I want to thank you for making
this technical LRM successful. I know that many have contributed to this
efforts to name them all. I want to thank the people who worked very
hard in the last few months and to the leadership (SV chairs and
champions).
Best Regards
Vassilios
Received on Thu Apr 29 11:33:21 2004