[sv-bc] Errata - forward typedef and generate

From: Dave Rich <David.Rich@synopsys.com>
Date: Thu May 06 2004 - 00:53:57 PDT
In Sept 2002, SV-BC-20 was proposed to eliminate an elaboration order dependency problem with forward typedefs and generate.
Ref: http://www.eda.org/sv-bc/hm/0061.html

This proposal was passed in an e-mail vote in Feb 2003. Ref: http://www.eda.org/sv-bc/hm/0482.html

However, there was an e-mail discussion after the proposal was originally sent out that did not get captured in the voting process.

I propose replacing the last paragraph in section 3.9

A typedef inside a generate shall not define the actual type of a forward definition that exists outside the scope of the forward definition

WITH

The actual type definition of a forward typedef declaration shall be resolved within the same local scope or generate block. Importing a typedef from a package into a local scope may also resolve a type definition.

Dave
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
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Received on Thu May 6 00:54:04 2004

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