[sv-bc] SV-BC Issue 24

IEEE 1364 says the following in section 12.2 on overriding parameter
values:

<quote>
A parameter declaration with no type or range specification shall
default to the type and range of the final override value assigned
to the parameter.

A parameter with a range specification, but with no type specification,
shall be the range of the parameter declaration and shall be unsigned.
An override value shall be converted to the type and range of the
parameter.

A parameter with a type specification, but with no range specification,
shall be of the type specified. An override value shall be converted to
the type of the parameter. A signed parameter shall default to the range
of the final override value assigned to the parameter.

A parameter with a signed type specification and with a range specification
shall be a signed, and shall be the range of its declaration. An override
value shall be converted to the type and range of the parameter.
</quote>

This uses the term "converted to the type and range" which I assume
means that the value is cast to the type of the parameter.

I think we should suggest to the IEEE to clarify this a bit for System
Verilog, but I don't see a need for any significant changes. Parameter
values are cast to the type of the parameter.

Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com
Received on Sun May 9 17:38:22 2004