[sv-bc] RE: SystemVerilog 3.1A Final LRM source

Vassilios,
 
I have added the Accellera board and SV subcommittees to this message, since
your action to fire me as the SystemVerilog LRM editor affect the board and
all the SystemVerilog committees and should have been brought to their
attention.
 
You are jumping to some conclusions that I do not feel are merited. I can
understand how you may have come to these false conclusions, due to the way
my name was used in a recent press article. Please do not take everything
you read in the press at face value--do some research first.
 
To set the record straight, I am not the spokesperson for this purported
SystemVerilog interoperability group. That title is something Richard
Goering came up with. Also, I did not "start" any such committee, as you
claim. I don't know where you got that impression. However, a presentation
on interoperability that I presented apparently served as a basis for the
request to have Accellera form a SystemVerilog subcommittee on
interoperability. I was also asked if I would accept a nomination to chair
such a committee. Because of my presentation and nomination, Richard
Goering called me to ask about the proposed committee. If you read the
article objectively, you will see that Richard correctly reported that said
that I fully expect Accellera to create this committee--it is the right
thing for Accellera to do. Richard did not report that I said accepting a
nomination to chair a proposed committee is not the same as being the chair
of the actual committee. I also told Richard that I feel there are much
more qualified engineers to chair the committee, once Accellera forms it
(which, again, is the right thing to do, and I have no doubt that it will
happen).
 
For the record, I do endorse the idea of an Accellera committee that meets
the two objectives that several user companies and EDA companies have
requested of Accellera. Those objectives are: First, to define a roadmap
for EDA companies to follow as they implement SystemVerilog. Second, to
create a test suite so that both EDA companies and end-users of
SystemVerilog can have the confidence that implementations actually work. I
endorse these two goals because in my work as a consultant and a trainer, I
am very anxious for all my customers and potential customers to very quickly
adopt SystemVerilog. However, I am told time and time again by my customers
that they cannot use SystemVerilog yet, because many of the tools in their
design flow do not support SystemVerilog. I am told--and it makes perfect
sense--that when a given construct, let's use structures as an example--is
supported by at least most of their tools, then they will encourage their
engineers to adopt that construct. My customers have also said that they do
the same thing for Verilog-2001 constructs, but tragically, different EDA
companies chose to implement Verilog-2001 constructs in different orders.
Therefore, even simple things like comma-separated sensitivity lists could
not be adopted for several years, because some key tool in the design flow
had not implemented that particular construct--even though that same tool
had implemented other constructs.
 
My presentation a few weeks ago at the Synopsys Interoperability Forum was
to suggest that if every EDA company followed the same order (note that is
"order", not "schedule") for implementing SystemVerilog constructs, then
users could adopt those constructs much more rapidly. Frankly, I made that
presentation figuring that I was just wasting my time. In my opinion, the
EDA vendor community has only every given lip service to true
"interoperability", and so I figured that my suggestions would fall on deaf
ears. I was astonished to learn a few weeks later that several user
companies and a handful of EDA vendors were taking the idea to Accellera to
request that a formal committee be formed on this very topic. To help
ensure that the concept was well understood, someone--and I do not know
who--put together a proposed plan of operation for the committee, and
gathered endorsements from a number of companies, in order to show the
Accellera board that this idea is viable, necessary, and wanted by the user
community. Part of this plan of operation is a proposed structural
organization of the committee with suggestions for chairs. That is where my
name came in. I as not directly involved in the development of this plan or
gathering endorsements for the plan. When Accellera does form this
committee, I am willing to serve as the chair if elected. There are other
members of the SystemVerilog committees within Accellera who would also be
good (better) chairs.
 
The full details of this proposed committee organization plan were not
reported in Richard's article, which leaves room for misunderstanding. Let
me make absolutely clear that the phased implementation plan is for 100% of
the SystemVerilog standard. It is not a subset in any way, shape, or form.
The expectation is that all EDA companies will support all of SystemVerilog.
The proposed plan also calls for the creation of a test suite for
SystemVerilog compliance. I am not completely sold on the idea of a test
suite, because it would be a very ambitious project. Two very positive
things would come out of such a suite, however, is that it will increase
user confidence that SystemVerilog as a standard, and it will prove that the
LRM is accurate (or uncover any errata/ambiguities).
 
Again, I have confidence that the Accellera board will do the right thing,
and form this interoperability committee. It is exciting to me to see the
EDA community aggressively take on implementing SystemVerilog. Some
companies hesitated a little longer than others, but all the major players
are now on the train. A uniform order of implementation will greatly speed
up user adoption of SystemVerilog. As soon as most tools support
structures, most engineers will begin using structures. As soon as most
tools support enumerated types, most engineers will begin using them, ...
 
Regarding being fired from my role as editor, that is your choice. I have
already sent a CD to Lynn with the source files, though she probably has not
received it yet. I will delete all the source files my computer now, per
your orders. Let me remind you that I am a member of the Accellera
SystemVerilog committees, which gives me the right to use the SystemVerilog
standard. Participation in these committees are open to all. I assume you
are not trying to fire me from being a participant in the standard.
 
Stu
~~~~~~~~~~~~~~~~~~~~~~~~~
Stuart Sutherland
stuart@sutherland-hdl.com
503-692-0898
 

  _____

From: Vassilios.Gerousis@infineon.com
[mailto:Vassilios.Gerousis@infineon.com]
Sent: Sunday, May 16, 2004 10:52 PM
To: Vassilios.Gerousis@infineon.com; lynn@accellera.org
Cc: dwsmith@synopsys.com; stuart@sutherland-hdl.com; dennisb@model.com
Subject: RE: SystemVerilog 3.1A Final LRM source

Hi Stu,
    Based on latest activities that you have started, your activities is
considered to be in conflict with Accellera standardization effort.
    Please make that you delete the source materials from your computer,
once Lynn has verified she has received the materials and she can read it
and verify its checksum.
    You are aware that you should not use any of the source material for the
new effort that you and Simon have started. I believe this is in direct
conflict with your previous role as SystemVerilog LRM Editor. Please make
sure you get reimbursement for the latest hours you have worked on.
 
Your activity as Accellera SystemVerilog Editor is now terminated.
 
Best Regards
 
Vassilios
Received on Mon May 17 09:21:29 2004