In describing the type checking restrictions on enumerated types,
section 3.10.3 (pg 20) contains the sentence "This restriction only
applies to an enumeration that is explicitly declared as a type".
This sentence was put in as an apparent reconciliation between the
original Vera enums and the SV 3.0 enums.
See http://www.eda.org/sv-ec/SV_3.1_Web/SVTestbench_2.2.pdf section 5
page 19
This exception seems to be inconsistent with the rest of the type
checking system, and it is not entirely clear what "explicitly declared
as a type" means.
I propose that this sentence be dropped. The authors of the original
donation concur.
Dave
-- -- David.Rich@Synopsys.com Technical Marketing Consultant and/or Principal Product Engineer http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625Received on Mon Jun 14 10:05:45 2004
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