My interpretation is that "import p::name;" brings a package defined
"name" into the local namespace, making it an alias for "p::name".
Therefore "name.subname" would be a valid reference to the subscope of
"p::name,subname". I see the the VHDL LRM makes an exception for
enumerated labels; the SV LRM should have done the same.
An intermediate typenames should not be imported without an explicit
statement. For example
package p;
typedef struct {int A} A_t
typedef struct {A_t B} B_t;
B_t B_s;
typedef B_t C_t;
endpackage
module top;
import p::B_s;
initial
B_s.B.A = 1; //legal
import p::C_t;
B_t foo; // illegal -name not imported
A_t bar; // illegal - name not imported
typedef byte B_t; // legal - no name conflict
endmodule
Steven Sharp wrote:
>A couple more questions I left out...
>
>If you import a struct type name, it seems pretty clear you want to import
>the names of the struct fields implicitly too. Otherwise you wouldn't be
>able to reference them without importing them explicitly. This seems
>necessary if you import a type name that is a typedef for a struct type
>also. Does this mean that you import the name of the type it is an alias
>for?
>
>And if one of the struct fields is a struct, then accessing its subfields
>would require importing that struct type implicitly. Should those names
>be imported also? And are only the field names imported, or is the type
>name imported also?
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant and/or Principal Product Engineer http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625Received on Mon Jun 21 15:56:12 2004
This archive was generated by hypermail 2.1.8 : Mon Jun 21 2004 - 15:56:18 PDT