Steve,
This issue reversed that decision. It was too late to make it into the
SV3.1a LRM
Steven Sharp wrote:
>>According to
>>
>> http://www.eda.org/sv-bc/display_issue.cgi?issue_num=38
>>
>>the following two statements have identical results
>>
>> typeA A = expr;
>> typeA A = typeA'(expr);
>>
>>
>
>Dave Rich said recently that the operand of a cast is
>self-determined. That is not consistent with this claim.
>
>The right-hand-side of an assignment is not self-determined.
>If the types are vectors, then its width is context-determined,
>with the width of the left-hand-side taken into account. So if
>the operand of a cast is self-determined, then these two statements
>do not have identical results.
>
>One of these claims is incorrect.
>
>Steven Sharp
>sharp@cadence.com
>
>
>
>
-- -- David.Rich@Synopsys.com Technical Marketing Consultant and/or Principal Product Engineer http://www.SystemVerilog.org tele: 650-584-4026 cell: 510-589-2625Received on Tue Jun 22 15:57:52 2004
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