[sv-bc] FW: [sv-ec] Quick poll for AMS extension to overload modules

Forward email for Geoffrey, Verilog-A Compact Modeling Chairman.

-----Original Message-----
From: geoffrey.coram@analog.com [mailto:geoffrey.coram@analog.com]
Sent: Thursday, July 08, 2004 3:46 PM
To: Gerousis Vassilios (CL DAT CS)
Cc: kcameron@altera.com; Srikanth.Chandrasekaran@motorola.com;
sv-ec@eda.org; verilog-ams@eda.org; VerilogA Device Modeling Reflector
Subject: Re: [sv-ec] Quick poll for AMS extension to overload modules

In response to Vassilios' request, I have created a document
http://www.eda.org/verilog-ams/htmlpages/public-docs/overloading.pdf
covering the three approaches for obtaining .model card features and
their advantages and disadvantages.

We will discuss that during the next Compact Modeling conference call,
scheduled for Tuesday July 13 at 9AM EDT. I will send the call-in
numbers to the AMS reflector and CC those on sv-ec who have expressed an
interest (sv-ec is public, and I've heard that conf call numbers have
been swiped). Please contact me if you want the information and don't
get it shortly after this message.

-Geoffrey
Received on Thu Jul 8 07:02:35 2004