RE: [sv-bc] RE: DASC-SC: result of vote on 1364 PAR

Hi Shalom,
        Here are few points that I hope will try to explain and possibly
make it clearer:

1- Accellera started on SV 3.1a errata prior to the actual transfer or
even prior to approval of the 1800 PAR. As an Accellera Organization, we
must maintain the support for our standards. We must support tool
developers with errata and clarification.

2- We are all in a transition period, where we will move the technical
work to the 1800. However this takes time. In the meantime, SV
committees will continue doing the work until the transfer is complete.
We have many infra-structure set up. We will use that for the support of
the 1800 WG. We are one team and not two separate teams.

Vassilios

-----Original Message-----
From: shalom@msil.sps.mot.com [mailto:shalom@msil.sps.mot.com] On Behalf
Of Shalom.Bresticker@freescale.com
Sent: Friday, July 09, 2004 4:23 PM
To: Gerousis Vassilios (CL DAT CS)
Cc: dennisb@model.com; stds-dasc-sc@eda.org; Sv-bc@eda.org;
ieee1800@eda.org
Subject: Re: [sv-bc] RE: DASC-SC: result of vote on 1364 PAR

Vassilios,

I think you have already explained this, but I am confused again.

With the establishment of IEEE P1800, what is the relationship of
SV-BC vs. P1800? Is there not a duplication or at least overlap of the
work?

Thanks,
Shalom

> Anyhow, we are all human, and if we made a mistake, please let
us
> know ASAP. The best way is for you to send me an email directly if you

> want and I will ensure that it is addressed. You can also join the
> sv-bc reflector and send your errata directly to this committee. This
> way you can also debate your points of views with the committee
> experts on both Verilog and SystemVerilog.

-- 
Shalom Bresticker                        Shalom.Bresticker
@freescale.com
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