Re: [sv-bc] always_comb question

From: Dave Rich <David.Rich@synopsys.com>
Date: Mon Jul 26 2004 - 10:38:06 PDT

Hi Shalom,

Comments below.

Dave

Shalom.Bresticker@freescale.com wrote:

>Thanks, Dave.
>
>I'm not sure that is relevant here.
>
>Even from a legalistic point of view, where we assume that each word is
>carefully chosen, 9.2.1 says, "shall not be written to by any other
>process", and does not mention the word "assignment".
>
>
One has to read the SV LRM with the understanding that is was written by
a committee, four committees in fact. So there are different choices of
words all over the place. I understand "written to" and "assignment" to
mean the same thing.

>Assume for the moment that a force is legal.
>
>Then, since I have written d as a function of a, The Right Thing to do
>would be to trigger the always_comb again in order to update a,
>even those d is only an intermediate variable and thus not in the implicit
>sensitivity list.
>
>
I think you meant to say "update *d*, even though *a* is only an
intermediate variable"

In any case, I disagree for two reasons. Had I explicitly wrote out the
sensitivity list, as many people would using Verilog, the sensitivity
list does not change when the force is applied. The other reason is that
making the always_comb block sensitive to changes on all intermediate
variables puts unnecessary overhead on top of updating all the
intermediate variables.

>Regards,
>Shalom
>
>
>On Sun, 25 Jul 2004, Dave Rich wrote:
>
>
>
>>Shalom,
>>
>>It will (or should) be legal to have a force. Section 5.6 says "A force
>>statement is neither a continuous or procedural assignment." for the
>>purposes of the rules about single continuous or multiple procedural
>>assignments. It should follow that a force is not considered an
>>assignment here too.
>>
>>Dave
>>
>>
>>Shalom Bresticker wrote:
>>
>>
>>
>>>Suppose I have an always_comb which uses an intermediate variable, like
>>>
>>>always_comb
>>>begin
>>> a = b & c ;
>>> d = a & e ;
>>>end
>>>
>>>My understanding is that "a" will not be in the implicit sensitivity list, as
>>>listed in the exceptions in 9.2.1(2):
>>>
>>>"any expression that is also written within the block or within any function
>>>called within the block."
>>>
>>>Also, it will be illegal to have an assignment to "a" in another process. 9.2
>>>says,
>>>"Variables on the left-hand side of assignments within an always_comb procedure,
>>>including variables from the contents of a called function, shall not be written
>>>to by any other processes."
>>>
>>>My question is, will it be illegal to do a "force" on "a", say in simulator
>>>interactive mode?
>>>
>>>If not, what will happen?
>>>
>>>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant and/or
Principal Product Engineer
http://www.SystemVerilog.org
tele:  650-584-4026
cell:  510-589-2625
Received on Mon Jul 26 10:38:13 2004

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