[sv-bc] Filing Errata

Hi, all,

        I was elected the SystemVerilog Errata Chair in the last P1800 committee meeting. In that role, I wanted to let everyone know about some upcoming deadlines that have been set by the P1800. In the next revision of SystemVerilog standard, we will be focusing on Errata. In order for an erratum to be guaranteed consideration for inclusion in the next balloted standard, the erratum must be filed by September 1, 2004 in the SystemVerilog Database:

http://www.eda.org/svdb

If your company has "filing" access to the database, please file all errata there. If your company does not have access, please send mail to the appropriate committee:

sv-bc@eda.org Design subset
sv-ec@eda.org Testbench subset
sv-cc@eda.org APIs
sv-ac@eda.org Assertions

with a subject line: Errata: <your issue title>

The chairs will see that the errata is entered into the database appropriately.

Errata entered after September 1, 2004 may be considered for resolution in the next balloted standard if time and priorities allow.

I look forward to working with each of you in this process.

Thanks,

Karen Pieper
Chair, P1800 Errata Technical Sub-Working Group
Received on Wed Aug 18 15:55:53 2004