Re: [sv-bc] Re: [sv-ec] SystemVerilog Packages - How are they used??

I believe you are correct. It should be a continuous assignment.
At 07:17 PM 8/18/2004 -0700, Andy Tsay wrote:
>Hi,
>
>The examples look fine, but I think the following assignment
> sum = add(a, b);
>should be
> assign sum = add(a, b);
>
>Thanks,
>Andy Tsay
>
>
>
>--- Francoise Martinolle <fm@cadence.com> wrote:
>
> > Cliff,
> >
> > I think that all the usages you show are legal.
> > An import clause can appear inside any declarative scope and outside
> module
> > definitions (in the compilation unit scope).
> >
> > At 07:53 PM 8/15/2004 -0700, Clifford E. Cummings wrote:
> > >Subject: SystemVerilog Packages - How are they used??
> > >
> > >Hi, All -
> > >
> > >Questions about package usage. In the 3.1a LRM we have good declaration
> > >examples but pretty poor usage examples and usage descriptions.
> > >
> > >I believe it is pretty clear that packages will be declared like separate
> > >modules and can include such things as data types, functions and tasks.
> > >
> > >Unclear is whether package import statements will be used inside or
> > >outside of modules (or both).
> > >
> > >Consider the following simple-minded examples:
> > >
> > >package MyPkg;
> > > typedef logic bit_t;
> > >
> > > function bit_t [8:0] add (bit_t [7:0] a, b);
> > > add = a + b;
> > > endfunction
> > >endpackage
> > >
> > >Now that I have a package with types, it seems like I have to use
> > >Verilog-1995 style module headers(?) to import the data type before I can
> > >use that type on the ports(?)
> > >
> > >module add2a (sum, a, b);
> > > import MyPkg::bit_t;
> > > output bit_t [8:0] sum;
> > > input bit_t [7:0] a, b;
> > >
> > > import MyPkg::add;
> > >
> > > sum = add(a, b);
> > >endmodule
> > >
> > >Or maybe I can use a cumbersome pkg::type notation in the output and
> input
> > >declarations(?) for ANSI-style Verilog-2001 headers(?)
> > >
> > >module add2b (
> > > output MyPkg::bit_t [8:0] sum, // this seems illegal??
> > > input MyPkg::bit_t [7:0] a, b);
> > >
> > > sum = MyPkg::add(a, b);
> > >endmodule
> > >
> > >Or can I use a wildcard package-import in front of the module (and now is
> > >this import statement valid for all modules compiled after this module
> > >??). Does this give me a $root global package import? This seems to be
> > >more VHDL-like (library ... uses ...)
> > >
> > >import MyPkg::*; // this seems illegal??
> > >module add2c (
> > > output bit_t [8:0] sum,
> > > input bit_t [7:0] a, b);
> > >
> > > sum = add(a, b);
> > >endmodule
> > >
> > >Any thoughts from the SystemVerilog package originators would be
> > >appreciated. Any references to where this is defined in the LRM would
> also
> > >be appreciated.
> > >
> > >Regards - Cliff
> > >
> > >
> > >----------------------------------------------------
> > >Cliff Cummings - Sunburst Design, Inc.
> > >14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> > >Phone: 503-641-8446 / FAX: 503-641-8486
> > >cliffc@sunburst-design.com / www.sunburst-design.com
> > >Expert Verilog, SystemVerilog, Synthesis and Verification Training
> > >
> > >
> >
> >
Received on Thu Aug 19 05:07:54 2004