[sv-bc] Errata: unique case evaluation order

Implementation of unique case in a simulator appears to require evaluation
of all of the case item expressions every time it is evaluated. Since
those case item expressions could include function calls which are impure
(have side effects or are influenced by non-argument variable values), or
new SystemVerilog assignment operators which have side effects, the order
of evaluation of those expressions could be significant.

The evaluation order should be defined, or explicitly stated to be
undefined.

On a related subject, when a second case item matches, a warning must
be issued. Can an implementation stop evaluating when it has determined
that a warning will be issued, or must it evaluate the remaining case items?
Again, the presence of side effects could make this significant.

On another related subject, there can be multiple case item expressions
attached to a single case item. If one of them matches, then the case item
matches, regardless of whether any of the others match also. Can an
implementation skip evaluation of the remaining case item expressions for a
case item once one of them is matched?

Steven Sharp
sharp@cadence.com
Received on Tue Aug 31 17:25:19 2004