RE: [sv-bc] Errata: variable initializers don't match Verilog-2001

Shalom,

As in well known, Verilog-2001 variable initializations are
nondeterministic. For example, a is not necessarily initialized
before the initial block in the following

          module test;
          reg a = 1;
          reg b;
          initial b = a + 1;
        endmodule

so b is not guaranteed to get a value of 2.

This follows from sections 6.2.1, 3.2.2, and 9.9, which say

     Variable declaration assignment is a special case of procedural
     assignment as it assigns a value to a variable. It allows an initial
     value to be placed in a variable in the same statement that declares
     the variable.

     If a variable declaration assignment is used, the variable will take
     the value as if the assignment occurred in a blocking assignment in
     an initial construct.

     The initial and always constructs are enabled at the beginning of
     a simulation. The initial construct shall execute only once and
     its activity shall cease when the statement has finished. ...
     There shall be no implied order of execution between initial and
     always constructs. The initial constructs need not be scheduled
     and executed before the always constructs.

The original SystemVerilog 3.0 donation from CoDesign fixed this
problem by eliminating the nondeterimism --

    Variable declaration assignments are initialized before any
    initial constructs.

This is totally backward compatible, because, obviously, no design
that already works under Verilog-2001 will be broken by the elimination
of the nondeterminism.

In SystemVerilog, the example above is guaranteed to assign b an
initial value of 2.

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of
Shalom Bresticker
Sent: Wednesday, September 01, 2004 4:51 AM
To: Steven Sharp
Cc: sv-bc@eda.org
Subject: Re: [sv-bc] Errata: variable initializers don't match
Verilog-2001

What was this referrring to?

Shalom

Steven Sharp wrote:

> This is well known, but has not been addressed in P1800.
>
> The semantics of variable initializers in SystemVerilog do not match the
> semantics defined in Verilog-2001. This is even explicitly acknowledged
> in the LRM.
>
> Steven Sharp
> sharp@cadence.com

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