Re: [sv-bc] Errata: inconsistent time literal rules

>From: Shalom.Bresticker@freescale.com
>
>One question: I did not understand the following sentence,
>near the end:
>
>> Changing a literal in an expression to a parameter defined to have the
>> same value as the literal has the effect of changing the behavior.
>
>Please clarify.

I was describing the second example again. To make the point clearer,
here is a variation of part of the example:

 `timescale 1ns/1ns
 module top;
 mid #(5.5ns) m();
 mid2 #(5.5ns) m2();
 endmodule

 `timescale 1ns/1ns
 module top2;
 parameter delay = 5.5ns;
 mid #(delay) m();
 mid2 #(delay) m2();
 endmodule

In top, the parameter override expressions are time literals. In top2,
the literals have been changed to a parameter defined as the same literal
value. This is the sort of thing you would do so you can conveniently
change the value in one place. But with the special case described in
the note, this difference would change the behavior. I think that most
users would find this very surprising.

Steven Sharp
sharp@cadence.com
Received on Wed Sep 1 13:31:40 2004