[sv-bc] Errata in SV 3.1a LRM Section 17.8: Syntax box 17.12 incorrect

Section 17.8, Syntax box 17.12 Variable assignment syntax

The contents of the syntax box do not have anything to do with variable
assignments

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Stuart Sutherland Sutherland HDL Inc.
stuart@sutherland-hdl.com 22805 SW 92nd Place
phone: 503-692-0898 Tualatin, OR 97062

Sutherland HDL, Inc. -- Training Engineers to be Verilog, SystemVerilog
and VHDL Wizards! http://www.sutherland-hdl.com
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Received on Wed Sep 1 23:18:44 2004