[sv-bc] Issue 0000119 Constant function definition should be expanded

I propose the following restrictions/enhancements for constant functions in System Verilog.

1) Functions with output, inout and ref ports cannot be constant functions.
2) Void functions cannot be constant functions
3) Functions with default arguments can be constant functions, provided that any default arguments
used in a constant function call are constant expressions.
4) Extend constant functions to include certain system function calls, like $bits and the array
query functions.
5) Constant functions cannot use any dynamic data types or overloaded operators.

I think the first 3 of these are straight forward. Since $bits and the array query functions are
already allowed in constant expressions, I don’t see any reason to not allow them in constant
functions.

The last restriction might be controversial.

Mark Hartoog
700 E. Middlefield Road
Mountain View, CA 94043
650 584-5404
markh@synopsys.com
Received on Tue Sep 7 21:22:54 2004