Re: [sv-bc] Built-in types are not packed arrays

>
> > I see your point, but section 4.2 is clearly distinguishing packed arrays
> > and built-in types. For example, you can't declare a packed array of bytes.
> >
> > byte legal [15:0];
> > byte [15:0] illegal;
>
> I regret all this special-casing for built-in types. Wouldn't be
> nice if SV simply defined a header file which contained:
>
> typedef logic signed [31:0] integer;
> typedef bit signed [31:0] int;
>
> etc., so that the predefined types behaved just like user types?

In a similar vein I previously suggested that the predefined types be
converted to predefined typedefs and an "untypedef" operation be added
so that "bit" and "logic" wouldn't have to be keywords, e.g. those types
would be something like:

  typedef _sv_logic_2 bit; // 0,1
  typedef _sv_logic_4 logic; // 0,1,Z,X

_sv_logic_2/4 are keywords. "untypedef" would let the compiler
forget the typedef again, e.g.:

  untypedef logic,bit; // forget logic & bit types

  `include "old_verilog.v" // include code that uses bit/logic as variables

  typedef _sv_logic_2 bit; // reinstate SV bit & logic
  typedef _sv_logic_4 logic;

The _sv_logic_* names are unlikely to clash with existing code. The untypedef
is also likely to be useful if SystemVerilog source is being parsed as a single
stream and different files happen to define disparate types with the same name
since it allows the scope of a root level typedef to be limited.

I agree with Paul that if you build the entire type system up from the basic
_sv_logic_* types, you can avoid inconsistent rules and clashing keywords,
with untypedef you could also do:

  typedef signed _sv_logic_4 [31:0] integer; // pre-defined typedef

  ... // my 32-bit CPU code
  
  untypedef integer;
  typedef signed _sv_logic_4 [63:0] integer;

  ... // my 64-bit CPU code

// want it to simulate faster -

  untypedef integer;
  typedef signed _sv_logic_2 [63:0] integer;

Probably not hard to implement and entirely backward compatible :-)

Kev.

Orig. post - http://www.eda.org/verilog-ams/hm/0697.html

> And I fondly remember "packed array of char" from pascal, but it looks
> like SV doesn't allow "packed array of byte".
>
> Paul

 
Received on Sat Sep 25 01:13:31 2004