How can we just "leave it the way it is", when the LRM claims that
SystemVerilog has pass-by-name semantics? The reason the proposal
does not change all references to "argument passing" is that they
are not all wrong. The argument passing in SystemVerilog can be
by value, by value-result, or by reference. The argument binding can
be by position or by name.
>
>043 ___Yes __ XXX _No
>http://www.eda.org/svdb/bug_view_page.php?bug_id=0000043
>
>I do not see what is being accomplished by this change. It does not change
all >references to 'argument passing' to 'argument binding', and it does not
mention >output arguments. I would rather leave it the way it is.
-- Brad
Received on Tue Oct 5 16:00:26 2004
This archive was generated by hypermail 2.1.8 : Tue Oct 05 2004 - 16:00:31 PDT