Re: [sv-bc] E-Mail Vote - Closes Midnight Oct 10

Hi Doug;

Requiring simulators to evaluate unique case branches and issue errors may cause false
errors to be reported due to simulation evaluation artifacts and timed signal propagations.

We have shown in early sv-ac discussions that error checking synchronized to a clock is
the safest way to avoid false failures.

Thus I think the change to warnings is prudent.

    Adam Krolnik
    Verification Mgr.
    LSI Logic Corp.
    Plano TX. 75074
    Co-author "Assertion-Based Design"
Received on Thu Oct 7 09:44:45 2004