[sv-bc] DataTypes: Changes for Section 18 "Hierarchy"

Proposed changes for Section 18 "Hierarchy".

Steven Sharp
sharp@cadence.com

Changes for Section 18 "Hierarchy"

In 18.1, CHANGE

 "An important enhancement in SystemVerilog is the ability to pass any data
  type through module ports, including nets, and all variable types including
  reals, arrays and structures."

TO

 "An important enhancement in SystemVerilog is the ability to pass a value
  of any data type through module ports, using nets or variables. This
  includes reals, arrays and structures."

In 18.8, CHANGE

 "With SystemVerilog, a port can be a declaration of a net, an interface,
  an event, or a variable of any type, including an array, a structure
  or a union."

TO

 "With SystemVerilog, a port can be a declaration of an interface, an event,
  or a variable or net of any allowed type, including an array, a structure
  or a union."

In 18.11.3, DELETE

 "- A port connection between a net type and a variable type of the same
    bit length is a legitimate cast."

In 18.12, CHANGE

 "SystemVerilog extends Verilog port connections by making all variable
  data types available to pass through ports."

TO

 "SystemVerilog extends Verilog port connections by making values of all
  data types on variables and nets available to pass through ports."

In 18.12.2, CHANGE

 "If a port declaration has a wire type (which is the default), or any
  other net type,"

TO

 "If a port declaration has a net type, such as wire,"

In 18.12.2, CHANGE

 "- An output can be connected to a net type (or a concatenation of net
    types) or a compatible variable type (or a concatenation of variable
    types).

  - An inout can be connected to a net type (or a concatenation of net
    types) or left unconnected, but not to a variable type."

TO

 "- An output can be connected to a net or variable (or a concatenation
    of nets or variables) of a compatible data type.

  - An inout can be connected to a net (or a concatenation of nets) of a
    compatible data type, or left unconnected, but cannot be connected to a
    variable."

In 18.12.4, CHANGE

 "The same rules for assignment compatibility are used for compatible
  port types for ports declared as an input or an output variable, or
  for output ports connected to variables."

TO

 "The same rules are used for compatible port types as for assignment
  compatibility."
Received on Wed Nov 3 14:12:28 2004