RE: [sv-bc] Re: Errata: inconsistent time literal rules

Brad,

This sentence was added in SV3.1 http://www.eda.org/sv-bc/hm/0422.html
(SV-BC-08-5) in response to an earlier question from Steven on section
3. See http://www.eda.org/sv-bc/hm/att-0060/02-02-09-16_minutes.txt.

I don't seem to be able to locate that document from Steven that has the
original question this sentence was supposed to address. If someone can
find it for me I will look into it some more.

Dave

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Wednesday, November 03, 2004 4:35 PM
To: sv-bc@eda.org
Subject: [sv-bc] Re: Errata: inconsistent time literal rules

In erratum 214

    http://www.eda.org/svdb/bug_view_page.php?bug_id=0000214

Steven Sharp points out various problems with the claim in
section 2.5 that

  "Note that if a time literal is used as an actual parameter to a
   module or interface instance, the current time unit and precision
   are those of the module or interface instance."

Even the form of this sentence is suspect, because it begins with
'Note', which usually indicates something informative, instead
of normative.

But, more importantly, this rule doesn't, in general, achieve its
goal of rescaling time literals. As Steven points out, in Verilog,
times values, like numeric values in most programming languages, are
just dimensionless numbers. They do not carry around their units with
them. This seems like an odd approach for a modeling language like
Verilog, but that's the way it is. For background on the issue, see --

http://research.microsoft.com/~akenn/units/RelationalParametricityAndUni
tsOf
Measure.pdf

To me, it seems reasonable to just strike this problematic sentence.

(In a future release, perhaps a true time data type could be added as
an enhancement.)

What are the counterarguments for retaining this sentence?

-- Brad
Received on Wed Nov 3 17:51:15 2004