Re: [sv-bc] Errata in SV 3.1a LRM Section 18.4: inconsistent use of error and warning

> > Nonblocking (no hyphen, ask Cliff) assignments are good for storage element
> > outputs,
> > then are not so good for combinational logic outputs.
> > Just the other day, I found a bug in code someone wrote due to using nonblocking
> > assignments
> > in combinational logic. Lucky for us, our linter found it.
>
> Indeed, I've read Cliff's papers on the assigns. What I was looking for was a
> way to avoid glitches. What is required is a way to make sure all the bits of
> the selector change at the same time, if at all. VHDL's event model would do
> this automcatically, but how can you get Verilog to do it?

You probably would not want to do this generally.
For example, we have a verification methodology in which we deliberately change
signals
at approximately, but not exactly, the same time, in order to spot various types of
problems
which escape you if you change them at exactly the same time.

The problem here is that the 'unique' controls the case statement, but not the case
statement's inputs
that come from another block. You would ideally want them to be independent.

> You could defer
> the uniqueness check to the "Observed" stage of the event queue, so it was
> only run on the last value of the case statement selector. Would that work?

Not completely, but it would help.

Shalom

--
Shalom Bresticker                        Shalom.Bresticker @freescale.com
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