[sv-bc] DataTypes: Proposed changes to section 5

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SECTION 5.1 Introduction:

ADD TO END OF SECTION:

SystemVerilog extends the set of data types that are available for modeling
Verilog storage and transmission elements. In addition to the Verilog-2001
data types, new predefined data types and user-defined data types can be
used to declare constants, variables, and nets.

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SECTION 5.2 Data declaration syntax:

ADD TO SYNTAX BOX:

 net_declaration ::=
     net_type_or_trireg [drive_strength|charge_strength] [vectored|scalared]
       data_type_or_implicit [delay3] list_of_net_decl_assignments;

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Add section called "Nets", right after section 5.4 Variables :

A net declaration begins with a net type that determines how the values
of the nets in the declaration are resolved. The declaration can
optionally include drive or charge strength, a vectored or scalared
indication, and delay values.

Verilog-2001 restricts the data type of a net to a scalar, a bit vector,
or an array of scalars or bit vectors. In SystemVerilog, any four-state
data type can be used to declare a net. For example:

     trireg (large) logic #(0,0,0) cap1;

     typedef logic [31:0] addressT;
     wire addressT w1;

     wire struct packed { logic ecc; logic [7:0] data; } memsig;

The data type of a net shall be one of the following:

   1) A four-state integral type

   2) An unpacked array or unpacked struct whose elements have data types
      that are allowed for a net

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SECTION 5.8.1 Equivalent types

CHANGE:

4) A typedef for an enum, unpacked struct, or unpacked union, or a class
   is equivalent to itself and variables declared using that type within
   the scope of the type identifier.

TO:

4) A typedef for an enum, unpacked struct, or unpacked union, or a class
   is equivalent to itself and to data objects that are declared using
   that data type within the scope of the data type identifier.
Received on Tue Nov 9 08:18:24 2004