[sv-bc] DataTypes: section 5, revision 2

Here is a revised version of the proposed changes to section 5, based on
feedback from our datatypes meetings. Please read carefully. It includes:

    - A definition of "data object", added to the first paragraph
      of 5.1

    - The rule for an implied data type of "logic" for a net
      if none is specified (in the new "Nets" section)

    - An attempt to improve the recursive definition of a valid data type
      for a net (in the new "Nets" section)

    - The statement that existing Verilog network semantics
      (resolution/strength/signedness) apply to nets of the new
      data types (in the new "Nets" section)

    - The lexical restriction on the use of "reg" after a net type
      keyword. This is also in the new "Nets" section. Since the
      SystemVerilog LRM does not have a lexical section, it is not
      clear where this one should go.

Just one small note about the first proposed change to section 5.8.1:
I think that there is a grammatical issue in the existing SystemVerilog
text. I kept the text in question, but I believe that it could be improved.

-----------------------------------------------------------------------------
SECTION 5.1 Introduction:

CHANGE:

There are several forms of data in SystemVerilog: literals (see Section 2),
parameters (see Section 21), constants, variables, nets, and attributes
(see Section 6)

TO:

There are several forms of data in SystemVerilog: literals (see Section 2),
parameters (see Section 21), constants, variables, nets, and attributes
(see Section 6). A data object is a named construct that has a data value
associated with it, such as a parameter or a variable or a net.

ADD TO END OF SECTION:

SystemVerilog extends the set of data types that are available for modeling
Verilog storage and transmission elements. In addition to the Verilog-2001
data types, new predefined data types and user-defined data types can be
used to declare constants, variables, and nets.

-----------------------------------------------------------------------------
SECTION 5.2 Data declaration syntax:

ADD TO SYNTAX BOX:

 net_declaration ::=
     net_type_or_trireg [drive_strength|charge_strength] [vectored|scalared]
       data_type_or_implicit [delay3] list_of_net_decl_assignments;

----------------------------------------------------------------------------
Add section called "Nets", right after section 5.4 Variables :

A net declaration begins with a net type that determines how the values
of the nets in the declaration are resolved. The declaration can include
optional information such as delay values and drive or charge strength.

Verilog-2001 restricts the data type of a net to a scalar, a bit vector,
or an array of scalars or bit vectors. In SystemVerilog, any four-state
data type can be used to declare a net. For example:

     trireg (large) logic #(0,0,0) cap1;

     typedef logic [31:0] addressT;
     wire addressT w1;

     wire struct packed { logic ecc; logic [7:0] data; } memsig;

If a data type is not specified in the net declaration then the data type
of the net shall be logic.

Certain restrictions apply to the data type of a net. A valid data type
for a net shall be one of the following:

   1) A four-state integral type

   2) An unpacked array or unpacked struct, where each element has
      a valid data type for a net

The effect of this recursive definition is that a net is comprised
entirely of four-state bits, and is treated accordingly. There is no change
to the Verilog-2001 semantics related to net resolution at the bit level,
the role of strength, or the treatment of the signed property across
hierarchical boundaries.

A lexical restriction applies to the use of the reg keyword in a net
or port declaration. A Verilog net type keyword shall not be followed
directly by the reg keyword. Thus, the following declarations are
in error:

    tri reg r;
    inout wire reg p;

The reg keyword can be used in a net or port declaration if there are
lexical elements between the net type keyword and the reg keyword.

-----------------------------------------------------------------------------
SECTION 5.8.1 Equivalent types

CHANGE:

3) An anonymous enum, struct, or union type is equivalent to itself among
   variables declared within the same declaration statement and no other
   types.

TO:

3) An anonymous enum, struct, or union type is equivalent to itself among
   data objects declared within the same declaration statement and no other
   ^^^^^^^^^^^^
   data types.
   ^^^^

CHANGE:

4) A typedef for an enum, unpacked struct, or unpacked union, or a class
   is equivalent to itself and variables declared using that type within
   the scope of the type identifier.

TO:

4) A typedef for an enum, unpacked struct, or unpacked union, or a class
   is equivalent to itself and to data objects that are declared using
                                  ^^^^^^^^^^^^
   that data type within the scope of the data type identifier.
        ^^^^ ^^^^
Received on Wed Nov 10 16:05:21 2004