RE: [sv-bc] DataTypes: Data type versus net type

From: Steven Sharp <sharp@cadence.com>
Date: Thu Nov 11 2004 - 11:57:42 PST

Stu,

Let me try to address this confusion in another way, to see if it makes
more sense.

You (and probably many other Verilog users) are accustomed to thinking of
a vector wire as an array whose element type is a wire, making it a bunch
of wires. You think of the net as the base element type from which the
vector is built, and start confusing it with the data type of the elements.

At the same time, you are accustomed to assigning the value of a wire or
parameter to a reg in Verilog. It seems natural to you that the value
of the wire or parameter can be read, and the "wire-ness" or "parameter-ness"
of that value will be discarded so that just the value is assigned to the
reg. Well, that concept of the value without the "wire-ness",
"parameter-ness" or "variable-ness" is what is meant by the term "data type".

We want to put data types on nets in SystemVerilog. We want to be able
to declare a net that is a struct and whose value can be assigned to a
variable of the same data type. To do that, we have to define data type in
a way that is independent of the "net-ness" and "variable-ness". If the
data type included the "net-ness", then it would not be type compatible with
any variable.

To make this work, the net type has to be treated as a qualifier on top
of a data type. You can take a "packed array of logic" and declare a wire
of that type, and you get a standard Verilog vector wire. Getting backward
compatibility involves setting the default base data type for a net to logic.
The declaration "wire [7:0] w;" is shorthand for "wire logic [7:0] w;"
The data type of the elements of the vector is "logic".

Sure, once you declare a net of that type, every element also has "net-ness".
But in the same way, every element of a vector parameter also has
"parameter-ness". That doesn't make the data type of the element be
"parameter". If you understand how "parameter" is not part of the data type,
you just have to transfer that same understanding to "wire".

Steven Sharp
sharp@cadence.com
Received on Thu Nov 11 11:57:46 2004

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