Re: [sv-bc] Does an input variable port of interface imply a ref if no modport?

Dave,

Thanks for the clarification. For an interface input variable port,
this is not a big distinction, because it's illegal to assign to an
input port variable (except via the implicit continous assignment
in the port connection), so it would also be illegal to assign to it
via a reference, making i.clk effectively a 'const' ref port.

However, for an interface *output* variable port, the distinction
would be significant, because interface instances are typically
connected to multiple module instances, and those instances could
communicate through the corresponding ref ports. For example,

interface IFC (input rst, output int count);
  always @(posedge rst) count = 0;
endinterface

module BOT(input clk, IFC i);
  always @(posedge clk) i.count++ ;
endmodule

module TOP #(P=8) (input rst, clk[P], output int count);
  IFC ifc(rst,count);
  for (genvar I=0; I< P; I++) begin
     BOT bot(clk[I], ifc);
  end
endmodule

-- Brad

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Rich,
Dave
Sent: Tuesday, November 09, 2004 12:31 PM
To: Brad.Pierce@synopsys.COM; sv-bc@eda.org
Subject: RE: [sv-bc] Does an input variable port of interface imply a
ref if no modport?

Yes, I believe interface declaration port variables and nets are
included in the list of 'objects' available to access through a
connected interface port.

In your example, the access i.clk is a ref port to module BOT. But note
that the single driver rule still applies, and that no other drivers can
be connected to the interface variable 'clk'. If you were to declare a
modport in IFC, 'clk' could be either a ref or input port.

Dave

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Monday, November 08, 2004 5:57 PM
To: sv-bc@eda.org
Subject: [sv-bc] Does an input variable port of interface imply a ref if
no modport?

At the end of 19.2.2, the LRM says "When an interface is referenced
as a port, the variables and nets in it are assumed to have ref and
inout access, respectively." Does this also apply to variables
and nets that are ports of the interface?

For example, when a port of an interface is of a variable type, such as

           interface IFC (input bit clk);

and an instance of the interface, say 'ifc', is connected without
using a modport,

           BOT bot(ifc);

then is the access of bot.ifc.clk ref, because of the
variable type with no modport, or is it input because of the
original port declaration? (Similarly, if the clk were a wire,
would bot.ifc.clk have inout or input access?)

Here's a full example --
           
interface IFC (input bit clk);
  wire w, x, y, z;
  ...
endinterface

module BOT(IFC i);
  // is i.clk a ref or an input?
endmodule

module TOP(input bit clk);
  IFC ifc(clk);
  BOT bot(ifc);
endmodule

-- Brad
Received on Fri Nov 12 11:00:14 2004