RE: [sv-ec] Re: [sv-bc] Deadline for detailed feedback on Data Types on Nets Proposal

In Verilog-2001 and prior, reg was used to declare a 4-value variable.
Logic was introduced to provide a future alternative to reg (and
spare us all one more question about how a register can behave as
combinational logic), but reg was not jettisoned to maintain backward
compatibility with Verilog, a significant feature of SV.

I don't think it is a 'feature' of SV that one can declare a struct
with a reg member, it's just that reg had to be dealt with somehow
to ensure backward compatibility. So in the absence of data type
extensions to net types and the continued focus on orthogonality of
objects the direct association of reg and logic was made.

Here's a terse summary of the decision on reg and logic:

http://www.eda.org/sv-bc/display_3.1a_issue.cgi?issue_num=40

This provides pointers to other meeting minutes with more information

I believe Jay was ok with this at the time because he was thinking
of a later enhancment that would reclaim reg as a means of
distinguishing a net data object from a variable data object.

Matt

>-----Original Message-----
>From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On
>Behalf Of Brad Pierce
>Sent: Monday, November 15, 2004 1:49 PM
>To: sv-bc@eda.org; sv-ec@eda.org
>Subject: [sv-ec] Re: [sv-bc] Deadline for detailed feedback on
>Data Types on Nets Proposal
>
>I tend to agree that 'reg' should not be a data type and that it
>would be better to use 'reg' instead of 'var'.
>
>Could someone please remind us again of the arguments for keeping
>'reg' as a data type that is equivalent to 'logic'?
>
>-- Brad
>
>
>
Received on Mon Nov 15 14:55:50 2004