RE: [sv-bc] DataTypes: wording for optional "var"

OK, this modified excerpt from the section 18 changes is hideous. I will
work on something better.

Steven Sharp
sharp@cadence.com

Changes for Section 18 "Hierarchy"

...

In 18.8, CHANGE

 "If the first port direction but no type is specified, then the port type
  shall default to wire. This default type can be changed using the
  `default_nettype compiler directive, as in Verilog."
  
TO

 "If the first port direction but no net type (or var keyword) or data
  type is specified, then the port shall default to a net of net type wire.
  This default net type can be changed using the `default_nettype compiler
  directive, as in Verilog."

In 18.8, CHANGE

 "For subsequent ports in the port list, if the type and direction are
  omitted, then both are inherited from the previous port. If only the
  direction is omitted, then it is inherited from the previous port. If
  only the type is omitted, it shall default to wire. This default type
  can be changed using the `default_nettype compiler directive, as in
  Verilog.

     // second port inherits its direction and type from previous port
     module mh3 (input byte a, b);
        ...
     endmodule"

TO

 "For subsequent ports in the port list, if the direction and the net type
  (or var keyword) and data type are omitted, then the direction and any
  net type and data type are inherited from the previous port. If the
  direction is omitted, but a net type (or var keyword) or data type is
  present, then the direction is inherited from the previous port. If the
  direction is present, but the net type (or var keyword) and data types
  are omitted, then the port shall default to a net of net type wire. This
  default net type can be changed using the `default_nettype compiler
  directive, as in Verilog.

     // second port inherits its direction and data type from previous port
     module mh3 (input byte a, b);
        ...
     endmodule

  For an inout port, if the net type is omitted, then the port shall default
  to a net of net type wire. This default net type can be changed using
  the `default_nettype compiler directive, as in Verilog.

     // the inout port defaults to a net of net type wire
     module mh2 (inout integer a);
        ...
     endmodule"

...
Received on Thu Nov 18 16:39:45 2004