Cliff,
You have described an enhancement you would like to the language. This
proposal does not provide that enhancement, and was not intended to. You
are suggesting that is a reason to vote against this proposal.
None of the other proposals that have been made to the BC have provided
that enhancement either, and were not intended to. And yet you have never
suggested that as a reason for voting against them.
This proposal does not conflict in any way with your desired proposal. In
fact, it removes one of the differences between variables and nets in
SystemVerilog, which brings us one step closer to what you have said you
wanted. The fact that it is a smaller step than you wanted is not a good
reason to reject that advance.
Steven Sharp
sharp@cadence.com
Received on Mon Nov 22 15:50:41 2004
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