RE: [sv-bc] SV-BC #110 - 2-State Divide by 0 question

I disagree with Doug. It might be a warning, but even
this I don't like. I would prefer that such decisions about
warnings and errors be left to the users via assertions. Let
the user write an assertion that the denominator is never 0
and let the user react accordingly.

Regardless, some default numerical result needs to be defined.
0 is a perfectly acceptable result to me. A simulator vendor
could also provide other options to users such as a random return
value or '1 or whatever.
  
Matt

>-----Original Message-----
>From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
>Behalf Of Warmke, Doug
>Sent: Tuesday, November 23, 2004 4:33 PM
>To: Clifford E. Cummings; sv-bc@eda.org
>Subject: RE: [sv-bc] SV-BC #110 - 2-State Divide by 0 question
>
>Cliff, others,
>
>How about saying something like:
>
> It shall be an error to perform a
> divide-by-0 operation on a 2-state object.
>
>I don't think any numerical result is correct.
>All 0's is too optimistic in my opinion.
>
>In light of the new datatypes work, my suggested wording
>could probably use a little wordsmithing. Volunteers?
>
>Regards,
>Doug
>
>> -----Original Message-----
>> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
>> Behalf Of Clifford E. Cummings
>> Sent: Tuesday, November 23, 2004 4:06 PM
>> To: sv-bc@eda.org
>> Subject: [sv-bc] SV-BC #110 - 2-State Divide by 0 question
>>
>> Hi, All -
>>
>> Don Mills and I have been asked to make a proposal for Issue
>> #110 on divide
>> by 0 in 2-state.
>>
>> I believe Don and I will propose that divide by 0 in 2-state
>> just gives
>> zero as a result. The problem is that the errata refers to a
>> 1364 section
>> and I am not sure where we should add this in the
>> SystemVerilog standard.
>> There is no addition-operator related section in the SV
>> standard to amend
>> with this information.
>>
>> Any suggestions?
>>
>> Regards - Cliff
>>
>> ----------------------------------------------------
>> Cliff Cummings - Sunburst Design, Inc.
>> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
>> Phone: 503-641-8446 / FAX: 503-641-8486
>> cliffc@sunburst-design.com / www.sunburst-design.com
>> Expert Verilog, SystemVerilog, Synthesis and Verification Training
>>
>>
>>
>
>
Received on Tue Nov 23 16:56:58 2004