RE: [sv-bc] SV-BC #110 - 2-State Divide by 0 question

>I looked at this a while ago and found that there is no easy way to
>define a 2-state division that is backward compatible with Verilog. For
>example

I had come to the same conclusion and was trying to find a way to
express it.

>I think it may be useful to use context determination rules similar to
>those used for width or signed determination.
>
>'100/0' in the example above should return 1'bx because it is being used
>in the context of a 4-state assignment.
>
>'B/0' would be a 2-state division because it is a self-determined
>expression.

I came up with a somewhat different solution that gives the same result
in almost all situations, and is simpler. In Dave's terms, you just treat
them all as 4-state contexts. Then there is no need for any new rules.

Except possibly for this division (and modulo) situation, the result of a
2-state and a 4-state calculation with 2-state inputs should always be the
same. So you can define all expressions as being calculated with 4-state
semantics. If you have a mix of 2-state and 4-state operands, you get the
right result automatically. An optimizer is free to throw away any extra
4-state work that isn't needed. With all 2-state operands, the optimized
4-state calculation should be identical to a 2-state calculation.

So division by zero would always give the 4-state result of X, which would
then be treated as a 4-state value by the rest of the calculation. If the
result was then assigned to a 2-state object, the value would be converted
from 4-state to 2-state.

>I would like to use the same rules for determining the result of an out
>of range array reference. Currently, the spec says to return the default
>un-initialized value. I think designers would rather see it return 'x
>when used in a 4-state context.

This makes sense too (except I would treat them all as 4-state contexts).

Steven Sharp
sharp@cadence.com
Received on Tue Nov 23 17:55:38 2004