[sv-bc] Erratum 325 -- "logic [P] [Q] id;" should be legal if "logic id [P][Q];" is

I've added erratum 325 about what I contend to be
an inconsistency between the syntaxes for packed and
unpacked arrays.

According to 4.2, "SystemVerilog accepts a single
number, as an alternative to a range, to specify
the size of an unpacked array, like C. That is,
[size] becomes the same as [0:size-1]."

Both for consistency and convenience, this same short
form should be allowed in the declaration of packed
arrays, too, although, of course, with the Verilog
numbering conventions.

It should be legal to write

     module m #(P=8) (input [P] in,
                      output [P] out);

instead of

     module m #(P=8) (input [P-1:0] in,
                      output [P-1:0] out);

just as one can already write

     module m #(P=8) (input in [P],
                      output out [P]);

instead of

     module m #(P=8) (input in [0:P-1],
                      output out [0:P-1]);

-- Brad
Received on Wed Nov 24 17:54:27 2004