[sv-bc] New Erratum #327: minor clarification on dimension ordering

Team,

Sorry to pile onto the heap, but there is one more trivial erratum
we found that I hope we can vote on tomorrow. It has been filed
as SV-BC #327 and there is a proposal attached:

     http://www.eda.org/svdb/bug_view_page.php?bug_id=0000327

For convenience, I am reproducing the proposal right here inline:

The existing text follows.
At issue is the last sentence, which talks about "first" and "second"
dimensions.
This is misleading and pretty much inaccurate no matter how it is read.

Thanks,
Doug

4.3 Multiple dimensions

Like Verilog memories, the dimensions following the type set the packed
size. The dimensions following the
instance set the unpacked size.

    bit [3:0] [7:0] joe [1:10]; // 10 entries of 4 bytes (packed into 32
bits)

can be used as follows:

    joe[9] = joe[8] + 1; // 4 byte add
    joe[7][3:2] = joe[6][1:0]; // 2 byte copy

Note that the dimensions declared following the type and before the name
([3:0][7:0] in the preceding declaration)
vary more rapidly than the dimensions following the name ([1:10] in the
preceding declaration).
When used, the first dimensions ([3:0]) follow the second dimensions
([1:10]).

REPLACE:
When used, the first dimensions ([3:0]) follow the second dimensions
([1:10]).

WITH:
When referenced, the packed dimensions ([3:0], [7:0]) follow the
unpacked dimensions ([1:10]).
Received on Mon Nov 29 15:52:23 2004