Re: [sv-bc] Proposal for compatibility problems with mixed Verilog/SystemVerilog code

Hi Stuart;

I've read your proposal and I have a few questions...

1. With the introduction of an end directive "`endkeywords", what shall the parser
    revert to? Can these directives be nested?

    `keywords "1364-2001"

    `keywords 1800-2005"

     ...

    `endkeywords
    `endkeywords

    Why follow the model of ifdef ... endif ?

2. Why the quotations marks on the name? We should allow for other names there so that
    we do not have to list all the legal versions now, hoping that we don't miss one.

3. You wrote:

"It affects all modules, primitives, interfaces, programs or packages that follow the
directive, even across source code file boundaries."

Allowing this directive to cross file boundaries does not IMHO provide any benefit. Some
compilers only read one file at a time while othes compile many. If one uses a single
file compiler, then every old file needs the directive. Also, given alternative orders
for compiling files, a simulation may stop compiliing due to a new file being compiled
while the compiler is in a compatibility keyword mode.

Yes, I know that the rest of the directives cross source code boundaries, but it would
be nice to fix this particularly for this compatibility option. If this can be done,
then it would also be nice to not follow the ifdef ... endif model and just terminate
the compatibility mode at the end of a compiled file (not the same as an included file.)
A user can then simply end the file and end the compatibilty mode, or be explicit and
use the "default" option.

     Thanks.

     Adam Krolnik
     Verification Mgr.
     LSI Logic Corp.
     Plano TX. 75074
     Co-author "Assertion-Based Design"
Received on Tue Nov 30 07:55:02 2004