RE: [sv-bc] Errata: variable initializers don't match Verilog-2001

Dave,

> I believe the testbench section of SV depends on the currently defined
> behavior,

Can you be more specific?

> and initialization of variables other than their defaults is
> testbench issue.

Not just a testbench issue.

Thanks,
Shalom

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Shalom Bresticker                        Shalom.Bresticker @freescale.com
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