Re: [sv-bc] Errata: variable initializers don't match Verilog-2001

Steven,

When you write that always constructs should 'execute' before initial blocks
and initializations at time 0, that term 'execute' could be misunderstood.

You mean if you have

always @(a or b) or always @(posedge clk), then you enter the always
and start waiting on the @(a or b) or @(posedge clk). For always_comb, you
mean to wait on the implicit sensitivity list.

Correct?

Shalom

On Thu, 9 Dec 2004 Shalom.Bresticker@freescale.com wrote:

> Your argument is convincing. I agree.
>
> Shalom
>
> > I think the best thing you can define for them is to require them to
> > execute before initial blocks (and initializers) at time zero. And the
> > P1800 LRM actually forbids that.
>
>

-- 
Shalom Bresticker                        Shalom.Bresticker @freescale.com
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